In future design of a multi-core processor, because of standstill of a solution for performance and power consumption, on-chip electrical interconnection becomes a bottleneck impeding system development. As silicon-based optoelectronic technologies become mature, optical communication becomes a most promising solution for interconnection of on-chip cores. However, because optical storage cannot be effectively integrated, and an optical logical processing technology is still not mature, communication resources need to be pre-allocated. In an optical network-on-chip (ONoC), an optical circuit exchange mechanism is usually used to implement communication between intellectual property (IP) cores. Before sending data to a destination node (a destination IP core), a source node (a source IP core) needs to reserve a communication resource, and a reserved communication resource is exclusively used by the data sent by the source node to the destination node, that is, another communications node cannot share the resource. Therefore, link utilization of optical circuit exchange is relatively low, and network congestion is relatively severe.
Currently, in an optical network-on-chip in which the optical circuit exchange mechanism is used, Mesh and Torus topologies are widely used. Network diameters (that is, maximum transmission hop counts) of optical networks-on-chip of an N×N scale implemented based on the Mesh and Torus topologies are respectively 2N−2 and N, and in addition, average hop counts of the two networks rapidly increase with expansion of a network scale, and consequently, severe congestion occurs in a process of resource reservation, and further network performance is affected.